1. Field of the Invention The present invention relates to an electrically erasable and programmable non-volatile semiconductor memory device (EEPROM) and the method of operating the same, and more particularly, to a flash EEPROM that can erase simultaneously a plurality of bytes of memory cells.
2. Description of the Background Art
EEPROMs are widely used such as in memory devices of IC cards since the stored information is electrically erasable and reprogrammable and the stored information can be retained even while power is off. An EEPROM includes a flash EEPROM that can simultaneously erase a plurality of bytes of memory cells (referred to as "flash memory" hereinafter).
FIG. 1 is a cross sectional view of a conventional flash memory cell. Referring to FIG. 1, a flash memory cell includes N.sup.+ type impurity regions 2 and 3 of high impurity concentration having a predetermined space therebetween on the, main surface of a P.sup.- type semiconductor substrate 1 of low impurity concentration. Impurity regions 2 and 3 implement a drain region and a source region, respectively. The flash memory cell further includes a floating gate 5 formed above a channel region 7 between impurity regions 2 and 3 with a very thin insulation film 4 of approximately 100 .ANG. thereunder, and a control gate 6 above floating gate 5 with an interlayer insulation film 8 therebetween. The flash memory cell has a double layered gate structure comprising floating gate 5 and control gate 6. Floating gate 5 is electrically isolated from impurity regions 2 and 3 and control gate 6 by means of insulation films 4 and 8, respectively.
The flash memory cell stores information according to the amount of accumulation of charge (electrons) injected into floating gate 5.
An inversion layer is not easily formed in channel region 7 when many electrons are injected in floating gate 5, resulting in a higher threshold voltage of the memory cell. When electrons are discharged from floating gate 5, an inversion layer is easily formed in channel region 7, resulting in a lower threshold voltage of the memory cell. The threshold voltage of a memory cell is the voltage applied to control gate 6, at which an inversion layer of low resistance is formed in channel region 7 between impurity regions 2 and 3 allowing current flow between impurity regions 2 and 3.
FIG. 2 is a graph showing the relationship between the voltage applied to control gate 6 and the charging/discharging state of electrons of floating gate 5. It is appreciated from FIG. 2 that the threshold voltage is high when electrons are injected into floating gate 5, whereby a voltage Vg applied to control gate 6 exceeding Vg0 causes a flow of source/drain current Ids. This state is called a write state and is defined as the state where data "0" is stored.
The threshold voltage is low when electrons are discharged from floating gate 5. In this case a voltage Vg applied to control gate 6 exceeding Vg1 causes a flow of source/drain current Ids (Vg1&lt;Vg0). This state is called an erase state and is defined as the state where data "1" is stored. A flash memory cell stores binary information of 1 and 0 by taking advantage of change in threshold voltage according to the accumulated amount of electrons (charge/discharge) of floating gate 5. The excessive erased state will be described afterwards.
A conventional data writing and erasing operation of the flash memory cell of FIG. 1 will be described hereinafter. In a normal reprogramming mode of data, the erase operation is first carried out, followed by the writing of data.
At the time of data writing, a writing voltage of approximately 6 V is applied to impurity region 2 serving as a drain region, and a high voltage of approximately 12 V is applied to control gate 6. Impurity region 3 is grounded. Under this state, an inversion layer is formed in channel region 7 where there is a flow of source/drain current Ids since the voltage of control gate 6 is sufficiently higher than threshold voltage Vg0. Here, avalanche breakdown occurs near impurity region 2 because of a high electric field to excite the electrons of the source/drain current to generate hot electrons. These hot electrons are accelerated towards floating gate 5 by the high electric field applied between control gate 6 and drain impurity region 2 to be injected into floating gate 5. This raises the threshold voltage of the flash memory cell to implement a writing state.
At the time of erase operation, a high voltage (approximately 12 V) is applied to source impurity region 3, and control gate 6 is grounded. Drain impurity region 2 attains a floating state. Here, a high electric field is generated between floating gate 5 and source impurity region 3 via a thin gate insulation film 4, whereby electrons from floating gate 5 are discharged to source impurity region 3 as tunneling current to drop the threshold voltage of the flash memory cell. Thus, the erasing state is realized.
The flash memory comprises a memory cell array having a plurality of flash memory cells of the structure of FIG. 1 arranged in a matrix manner. A memory device is implemented by storing desired data in the memory cell in the memory cell array.
FIG. 3 shows the entire structure of a conventional flash memory. Referring to FIG. 3 a flash memory 100 comprises a memory cell array 110 having a plurality of flash memory cells arranged in a matrix of rows and columns. For the sake of simplicity, memory cell array 110 is shown to comprise four flash memory cells 16, 17, 18, and 19 arranged in two rows and two columns in FIG. 3. Memory cell array 110 comprises a word line W (W0, W1) to which memory cells of one row are connected, and a bit line B (B0, B1) to which flash memory cells of one column are connected.
Flash memory 100 further comprises an address buffer 8 to receive an address signal (this may be an external applied signal or may be applied from a processing unit formed on the same chip) for generating an internal address signal, an X decoder 12 for decoding an internal row address signal from address buffer 8 to select a corresponding word line, a Y decoder 9 for decoding an internal column address signal from address buffer 8 for generating a column select signal Y (Y1, Y0) for selecting a corresponding column in memory cell array 110, a sense amplifier 15 for detecting and amplifying the stored data in the memory cell selected by X decoder 12 and Y decoder 9, a writing circuit 20 for writing information into a selected memory cell, and a data input/output buffer 21 for carrying out data input/output with an external source.
A column selector gate circuit 120 is provided between sense amplifier 15 and writing circuit 20, and bit line B (B0, B1) of memory cell array 110 for connecting a corresponding bit line to sense amplifier 15 or writing circuit 20 according to column select signal Y from Y decoder 9. Column selector gate circuit 120 is shown to comprise a Y gate transistor 10 provided corresponding to bit line B0 to attain a conductive state in response to column select signal Y0, and a Y gate transistor 11 provided corresponding to bit line B1 to attain a conductive state in response to column select signal Y1.
Sense amplifier 15 applies a reading voltage to a selected bit line at the time of data reading. Sense amplifier 15 detects the presence/absence of current flowing through that bit line to amplify the information in the selected memory cell, whereby the amplified signal is transmitted to the output circuit included in data input/output buffer 21. The data sensed/amplified by sense amplifier 15 is also supplied to a write/erase control circuit 25 for the verify operation that will be described afterwards. Writing circuit 20 responds to the write data from the input buffer included in data input/output buffer 21 to apply a voltage corresponding to the write data to the selected bit line.
Flash memory 100 further comprises a write/erase control circuit 25 responsive to external control signals, i.e. a chip enable signal CE, an output enable signal OE, and a write enable signal WE, for generating various internal control signals and for controlling the write/erase operation, a Vpp/Vcc switching circuit 22 responsive to a select signal of write/erase control circuit 25 for selecting an externally applied high voltage Vpp or an operating power supply voltage Vcc, a word line voltage modifying circuit 23 for modifying the voltage applied to a word line according to the operation mode of the flash memory under the control of write/erase control circuit 25, and a source potential generating circuit 24 for applying a voltage to each source of the memory cell according to the operation mode under the control of write/erase control circuit 25.
In memory cell array 110, one source line Si (S1, S2) is provided for one unit of memory cells that can be accessed at one time (for example 1 byte). Source line Si is connected to source potential generating circuit 24 via a common source line S. More specifically, memory cells of one access unit arranged in the column direction are connected to the same source line Si. The structure of providing one source line for each access unit of memory cells allows reduction in the wiring area for source lines to achieve larger scale integration.
The voltage generated from word line voltage modifying circuit 23 is applied to X decoder 12. X decoder 12 transmits this voltage to the selected word line as a word line driving signal.
High voltage Vpp is normally 12 V, and operating power supply voltage Vcc is normally 5 V.
Source potential generating circuit 24 generates high voltage Vpp at the time of erasing mode which is transmitted to source line Si. At the time of writing and reading operation mode, source potential generating circuit 24 connects source line Si to ground potential.
Writing circuit 20 provides a writing high voltage (lower than high voltage Vpp, approximately 6 V) at the time of writing data 0 corresponding to write mode, and generates a voltage of ground potential level at the time of writing data 1 corresponding to the erase mode.
Word line voltage modifying circuit 23 is responsive to various operation modes to generate high voltage Vpp, operating power supply voltage Vcc, write verify voltage Vwr, erase verify voltage Ver.
FIG. 4 shows a specific structure of word line voltage modifying circuit 23 of FIG. 3. Referring to FIG. 4, word line voltage modifying circuit 23 comprises resistors 35 and 36 connected in series between node ND1 receiving voltage Vpp/Vcc from Vpp/Vcc switching circuit 22 and ground potential, and an n channel MOS (insulation gate type field effect) transistor 34. Here, "Vpp/Vcc" refers to either voltage Vpp or Vcc. Resistors 35 and 36 have resistances of R1 and R2, respectively. Transistor 34 responds to a verify signal VRFY to attain a conductive state. Voltage Vpp/Vcc or a verify voltage is provided from node ND2 which is the connection node of resistors 35 and 36.
Verify signal VRFY attains an active state of an H level (logical high) at the verify cycles of verifying whether the memory cell is reliably erased at the time of erase operation mode, and of verifying whether write data is reliably written into a selected memory cell at the time of data write operation.
Word line voltage modifying circuit 23 further comprises an inverter circuit 37 for inverting verify signal VRFY, a Vpp switch 38 activated in response to the output of inverter 37 to transmit voltage Vpp/Vcc, a comparison circuit 47 for comparing the voltage on an input line 47a and the voltage on an input line 47b, a p channel MOS transistor 29 attaining a conductive state in response to the voltage on output line 47c of comparison circuit 47 to transmit voltage Vpp/Vcc to X decoder 12 (refer to FIG. 3) via signal line 23a, and an n channel MOS transistor 30 responsive to the output of inverter circuit 37 to reset output line 47c to ground potential.
Comparison circuit 47 comprises a p channel MOS transistor 26 responsive to an output signal of Vpp switch 38 for selectively transmitting voltage Vpp/Vcc to node ND3, a p channel MOS transistor 27 provided between node ND3 and node ND4, a p channel MOS transistor 28 provided between node ND3 and node ND5, an n channel MOS transistor 32 provided between node ND4 and the node ND6, an n channel MOS transistor 31 provided between node ND5 and node ND6, and an n channel MOS transistors 33 provided between node ND6 and ground potential.
Node ND4 is connected to the gates of transistors 27 and 28. As a result, transistors 27 and 28 implement a current mirror circuit where the same amount of current flows through transistors 27 and 28 if their sizes are the same. The gate of transistor 31 is connected to node ND2 via input line 47a. The gate of transistor 32 is connected to signal line 23a via input line 47b. The gate of transistor 33 is supplied with verified signal VRFY. Comparison circuit 47 responds to verify signal VRFY to be activated, and functions to establish the same voltage on signal line 47a and on signal lines 23a and 47b.
FIG. 5 shows a specific structure of Vpp switch 38 of FIG. 4. Referring to FIG. 5, Vpp switch 38 comprises an inverter circuit 145 for inverting an input signal (Vpp switch activation signal), an n channel MOS transistor 143 having its gate connected to operating power supply voltage Vcc for transmitting the output of inverter circuit 145, a p channel MOS transistor 141 and an n channel MOS transistor 144 forming an inverter for inverting the signal transmitted from transistor 143, and a p channel MOS transistor 142 responsive to the signal potential on an output node ND10 for transmitting voltage Vpp/Vcc to node ND11.
Voltage Vpp/Vcc is transmitted to one conduction terminal (source terminal) of transistor 141. When node ND11 attains a high voltage Vpp level, transistor 143 serves to prevent the high voltage Vpp from being applied to the output of inverter circuit 145. Prior to the description of the entire operation of a flash memory, the operation of word line voltage modifying circuit 23 will be described hereinafter with reference to FIGS. 4 and 5.
When verify operation is not carried out, i.e. at the time of the modes of erase operation, data writing, and data reading operation, verify signal VRFY is "low" of ground potential level. Under this state, transistors 33 and 34 are off, and transistor 30 is turned on by a "high" signal (operating power supply voltage Vcc level) from inverter circuit 37.
When transistor 33 is OFF, comparison circuit 47 attains an inactive state since current does not flow thereto. When transistor 34 is OFF, current will not flow across resistors 35 and 36, whereby voltage Vpp/Vcc applied to node ND1 is provided from node ND2. When transistor 30 is ON, the potential of signal line 47c attains a ground potential level of L to turn on transistor 29, whereby voltage Vpp/Vcc is transmitted to signal line 23a.
At the time of verify operation mode, verify signal VRFY attains the operating power supply voltage Vcc level of H. This turns on transistors 33 and 34, and transistor 30 is turned off by the output of inverter circuit 37. Under this state, current flows across resistors 35 and 36 so that voltage Vpp/Vcc applied to node ND1 is resistor-divided by resistances R1 and R2 to be provided from node ND2. The voltage of node ND2 is applied to the gate of transistor 31 of comparison circuit 47 via signal line 47a. Since transistor 33 is ON, comparison circuit 47 carries out the comparison operation.
Because the output of inverter 37 is L, the output of inverter circuit 145 is H in Vpp switch 38,. This turns on transistor 144, whereby the potential of node ND10 attains a low level. Here, voltage Vpp is applied to transistor 141. When the potential of node ND11 attains the level of voltage Vcc, transistor 141 is turned on so that current flows via transistors 141 and 144. If the potential level of node ND10 attains a low level, transistor 142 is turned on so that voltage Vpp/Vcc is transmitted to node ND11. Thus, transistor 141 is reliably turned off, and node ND10 attains a L level of ground potential. In response, transistor 26 of comparison circuit 47 is turned on, whereby the potential of node ND3 attains the level of Vpp/Vcc.
Transistor 31 is turned on in response to the voltage on input line 47a (referred to as "erase verify voltage Ver" hereinafter). The potential of node ND5 takes a value where the voltage between ND3 and node ND6 is resistor-divided by the ON resistances of transistors 28 and 31. At this time, the voltage on output line 47c becomes higher than the ground potential level. In response, transistor 29 approaches the OFF state to have a greater resistance. The voltage on signal line 23a becomes lower than voltage Vpp/Vcc. The voltage on signal line 23a is provided to the gate of transistor 32. In response to the decrease of voltage on signal line 23a, transistor 32 will have a greater resistance to raise the potential of node ND4.
The rise of potential in node ND4 is fedback to the gates of transistors 27 and 28 to result in a greater resistance for transistors 27 and 28. Therefore, the amount of current flowing through transistors 27 and 28 becomes lower. This reduces the potential of node ND5 to lower the resistance of transistor 29 via a signal line 47c, whereby the voltage on signal line 23a is raised.
In other words, comparison circuit 47 operates to equalize the erase verify voltage Ver applied to input line 47a and the voltage on signal line 23a. The voltage transmitted to the X decoder via signal line 23a depends on resistances R1 and R2. An erase verify voltage of a desired voltage level can be generated by setting appropriate resistances of R1 and R2.
When verify signal VRFY is at a low level, node ND11 in Vpp switch 38 of FIG. 5 attains a ground potential low level. A voltage of Vpp/Vcc level is generated in node ND10 to turn off transistor 142. Transistor 26 of comparison circuit 47 is set to an off state since the potentials of the source and gate become identical regardless of voltage Vpp/Vcc. Even if signal line 47c is reset, current will not flow from signal line 47c to transistor 30.
The entire operation of a flash memory will be described hereinafter with reference to FIG. 3. The data writing operation to a memory cell is initiated by a control signal, i.e. chip enable signal CE and write enable signal WE. The writing operation of external data to a selected memory cell comprises an erase operation mode for carrying out erasing of a memory cell, and a write operation mode for actually writing data into a selected memory cell. In the following description, the term "programming mode" refers to both the erase operation mode and writing operation mode. The write operation mode will be described first.
At the time of write operation mode, Vpp/Vcc switching circuit 22 generates a high voltage Vpp under the control of write/erase control circuit 25. Word line voltage modifying circuit 23 has a "low" verify signal to generate a high voltage Vpp which is provided to X decoder 12. Source potential generating circuit 24 connects common source line S to ground potential under the control of write/erase control circuit 25. Thus, each source line Si (S1, S2) is set to ground potential.
Address buffer 8 has the address strobe timing determined by write/erase control circuit 25 to generate an internal address signal from an applied address signal. It is assumed that word line W0 and bit line B0 are selected. In this case, X decoder 12 transmits to word line W0 high voltage Vpp from word line voltage modifying circuit 23. Y decoder 9 pulls up column select signal Y0 to a high level. The voltage of a high level column select signal Y0 is greater than operating power supply voltage Vcc for passing a write high voltage which is greater than power supply voltage Vcc. The implementation of Y decoder 9 for generating a high voltage at the time of writing operation may employ the implementation of generating a voltage by resister-dividing voltage Vpp, as in the case of word line voltage modifying circuit 23 of FIG. 4.
Data input/output buffer 21 receives an externally applied write data D to generate and provide to writing circuit 20 an internal data under the control of write/erase control circuit 25. Also under the control of write/erase control circuit 25, writing circuit 20 generates a write high voltage (approximately 6 V in general) in writing data 0. In writing data 1, a signal of ground potential level is generated. Column select signal Y0 causes Y gate transistor 10 in column selector gate 120 to conduct, whereby a write high voltage is applied to bit line B0. Thus, a high electric field is applied between the control gate and the drain of memory cell 16, whereby injection of hot electrons to the floating gate is carried out. This induces a rise in threshold voltage in memory cell 16 to establish a writing mode for storing data 0. When data 1 is to be written, hot electrons are not generated since a high voltage is not applied to the drain, and injection/ejection of charge towards/from the floating gate does not occur. Actual writing of data 1 is not carried out since all the memory cells are set to an erase state (state of data 1 stored) prior to the data writing operation.
The erase operation mode carried out prior to the data writing operation for setting the memory cell into an erased state will be described hereinafter with reference to the flow chart of FIG. 6.
Write/erase control circuit 25 enters an erase operation mode when chip enable signal CE and write enable signal WE both become active. In this erase operation mode, the flash memory has all the data in all the memory cells erased simultaneously. At this time, a pre-erase writing operation is carried out to establish a similar threshold voltage for all the memory cells (refer to FIG. 6 step S501). The pre-erase writing is the writing of data 0 into all the memory cells.
In the pre-erase writing cycle, writing circuit 20 generates a write high voltage. X decoder 12 selects all the word lines (W0, W1). Y decoder 9 sets all the column select signals Y (Y1, Y0) to an active state. Word line voltage modifying circuit 23 generates a high voltage Vpp which is provided to X decoder 12. Source potential generating circuit 24 generates ground potential which is provided to common source line S. As a result, write high voltage is applied to the drains, and high voltage Vpp is applied to the control gates of all the memory cells of 16, 17, and 18. The source is set to ground potential. Thus, all the memory cells are set to a writing state where data 0 is written therein. This writing operation in all the memory cells to raise the threshold voltage is called a pre-erase writing operation.
On completion of this pre-erase writing operation, all the memory cells are set to an erase state. At this time, X decoder 12 turns all the word lines W0, W1 into a non-selected state having a potential of ground potential level. Y decoder 9 is inactive so that column select signals Y0 and Y1 are set to "low". Thus, bit lines B0 and B1 are set to a floating state. Source potential generating circuit 24 generates high voltage Vpp for a predetermined time under the control of write/erase control circuit 25 to provide the voltage to common source line S. This high voltage Vpp generated for a predetermined time is a pulse signal referred to as an erasing voltage pulse. The application of this erasing voltage pulse causes electrons to be drawn from the floating gate to the source by tunnel effect in each memory cell. As a result, the threshold voltage in the memory cell is lowered (step S502).
Then, a verify operation is carried out for verifying whether the memory cell is set to an erased state. In the verify cycle, source potential generating circuit 24 connects common source line S to ground potential (step S503).
Next, X decoder 12 and Y decoder 9 selects a memory cell of address 0 (step S504). An erase verify voltage Ver from word line voltage modifying circuit 23 via X decoder 12 is transmitted to the word line to which the selected memory cell of address 0 is connected. More specifically, verify signal VRFY is high and verify voltage Ver is generated from signal line 23a in FIG. 4.
It is assumed that the memory cell of address 0 is memory cell 16. The data in memory cell 16 of address 0 is sensed and amplified by sense amplifier 15 to be provided to write/erase control circuit 25. Write/erase control circuit 25 makes determination whether the data provided from sense amplifier 15 is data 1 indicating an erased state (step S506). A read out data of "1" indicates that the threshold voltage of that memory cell is lower than erase verify voltage Ver. This means that memory cell is in an erased state. Write/erase control circuit 25 then makes determination whether the address of the selected memory cell is the last address or not (step S507). If the address of the current selected memory cell is not the last address, the address is incremented by 1 (step S508) and the control returns to step S506. This operation is repeated, and the erase operation mode is completed when determination is made of a memory cell of the last address storing data 1 (step S507).
When determination is made in write/erase control circuit 25 that the read out data is not 1 in a memory cell of an address at step S506, the control returns to step S502 since that memory cell has a threshold voltage greater than a desired erase verify voltage and is verified as to be not in an erased state. An erase voltage pulse of high voltage is applied from source potential generating circuit 24 to the source line, whereby the erase operation for each memory cell is carried out. Then, the memory cell of address 0 is selected again to have its stored data read out. This operation is repeated until the threshold voltage of all the memory cells are verified to be below the erase verify voltage.
Erase verify voltage Ver is set lower than the voltage transferred to the word line in a normal data read out operation.
In a flash memory cell, the erase state is realized by the discharge of electrons from the floating gate. The electron discharge is carried out by generating tunneling current between the, floating gate and the source region. The discharged amount of electrons depends upon the level and width of the erase voltage pulse applied between the floating gate and a source region and the number of times of that application.
In the above-described erase operation mode, pre-erase writing is carried out to make uniform the threshold voltage of the memory cells, followed by lowering the threshold voltage of the memory cell less than a predetermined value (erase verify voltage) by applying an erase voltage pulse and carrying out verify operation.
The source line is provided in common for a unit of access memory cells (for example 1 byte). An interconnection is required for the connection of the source region and the source line, incuring a source resistance. There is an occurrence of different source potential in the memory cells of one access unit caused by this source resistance. This means that even memory cells in one access unit have different discharge amount of electrons at the time of its erase operation, resulting in variation in erase characteristics.
In a memory cell array, the gate insulation film or the channel region may vary depending on variation in the manufacturing process as a local factor. This also is responsible for variation in the erase characteristics of a memory cell.
In the event of variation in erasing characteristics of a memory cell, electrons will be drawn excessively from the floating gate of a memory cell by an application of an erase voltage pulse.
This state of electrons excessively drawn from the floating gate is called an excessive erase state. The threshold voltage of the excessively erased memory cell shows a depletion state. This "depletion state" refers to a state where source/drain current flows to the memory cell even when ground potential is applied to the control gate.
When memory cells having the threshold voltage set to be within a predetermined range (pre-erase writing) are erased to set the threshold voltage of each memory cell to be less than the erase verify voltage Ver, excessively erased memory cells are present as represented by the broken lines of FIG. 7. When a not-erased cell is found at the time of verify operation, an erase voltage pulse is applied again. This pulse will be applied also to the cells already taking an erased state, resulting in excessive erase.
The presence of such excessively-erased memory cells leads to a problem that correct data reading cannot be carried out.
The problem of this excessively erased memory cell will be described with reference to FIG. 8. Referring to FIG. 8, memory cells FM1, FM2 and FM3 are disposed at the crossings of three word lines WL1, WL2, WL3; and a bit line BL. Memory cell FM1 stores data "1" attaining an erased state. Memory cell. FM2 attains an excessive-erased state, storing data "11". Memory cell FM3 attains a writing state, storing data "0".
At the time of data reading, a voltage approximating operating power supply voltage Vcc is transmitted to a selected word line according to an applied address, and a reading voltage is applied to bit line BL for the generation of current. Data reading is carried out by detecting the presence/absence of current on bit line BL by a sense amplifier. It is assumed that memory cell FM2 attains an excessive-erased state. This means that memory cell FM2 always conducts regardless of whether word line WL2 is selected or not. Consider the state where memory cell FM3 is selected. Memory cell FM3 stores data "0" and is non-conductive even if word line W3 is selected. However, memory cell FM2 is conductive even if word line WL2 is not selected so that current flows from bit line BL to source line SL, resulting in a determination that memory cell FM3 stores data "1" which represents an erased state. This means that data "1" is erroneously read out instead of data "0". A flash memory of high reliability cannot be obtained.
In writing data into a memory cell, a writing operation mode for actually writing data into a memory cell is carried out after the above-described erase operation mode.
As shown in FIG. 9, the programming mode requires a sequence for carrying out the erase operation mode, and a sequence for carrying out the write operation mode. The erase operation mode is similar to that shown in the flow of FIG. 6. FIG. 9 shows a more simplified erase operation mode. Briefly, in the operation mode, the pre-erase writing (step S602), is carried out an erase pulse is applied to decrease the threshold voltage in all memory cells (step S603), an erase verify operation is carried out for determining whether the threshold voltage of the memory cell is below a predetermined value (step S604), to complete the erase operation mode when confirmation is made that all the memory cells are under an erased state (step S606).
Following this erase operation mode, a writing operation mode is commenced (step S608). A write data is applied to writing circuit 20, whereby a write pulse is applied to the memory cells having data "0" written therein by writing circuit 20 (step S610). This write pulse applies a predetermined writing high voltage in a pulse-manner to a bit line while applying high voltage Vpp to a word line. Upon applying this write pulse, the contents of the written data is read out. When reading out the contents of the written data, a write verify voltage slightly higher than operating power supply voltage Vcc (the voltage level applied to the word line at the time of normal reading mode) to the selected word line. When the read out data of the memory cell does not match the written data, a write pulse is applied again to the selected memory cell to carry out the write verify operation again (step S612). The match/mismatch detection of the write data and the stored data of the selected memory cell is carried out by write/erase control circuit 25 shown in FIG. 3. If the stored data and the write data match in the writing verify cycle, the writing operation of data into a selected memory cell is completed. This writing operation mode is carried out for all the memory cells to be written. There was a problem that the programming mode is time consuming in a conventional flash memory.
In the erase operation mode, an erase verify operation is required to determine whether each memory cell is set to an erased state after all the memory cells are subjected to the erasing operation. This is responsible for the long time period required for the erase operation mode.
In writing operation mode, writing is carried out for each unit of data writing (normally 1 byte unit). Data writing is carried out for not just 1 byte of memory cells, but sequentially for memory cells of a plurality of bytes, resulting in a longer time for writing mode operation.
Although the erase operation mode and the write operation mode are both executed under the control of the write/erase control circuit, the erase operation mode and the write operation mode respectively have an operation sequence independent of each other. Therefore, the control operation is complicated and the program operation burdensome.